Welcome![Sign In][Sign Up]
Location:
Search - vhdl controller

Search list

[Windows DevelopVHDLgdewrrrrrrrrrrrr

Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言,实现对路口交通灯系统的控制器的硬件电路描述,通过编译、仿真,并下载到CPLD器件上进行编程制作,实现交通灯系统的控制过程。EDA技术是用于电子产品设计中比较先进的技术,可以代替设计者完成电子系统设计中的大部分工作,而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持,既缩短了研发周期,又大大节约了成本,受到了电子工程师的青睐。实现路口交通灯系统的控制方法很多,可以用标准逻辑器件、可编程序控制器PLC、单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持,在一定程度上增加了功能修改及系统调试的困难。因此,在设计中采用EDA技术,应用目前广泛应用的VHDL硬件电路描述语言,实现交通灯系统控制器的设计,利用MAXPLUSⅡ集成开发环境进行综合、仿真,并下载到CPLD可编程逻辑器件中,完成系统的控制作用。-the current design was chosen over a wide range of VHDL hardware description language circuit. Implementation of traffic lights at the junction of the controller hardware circuit description, compiler, simulation, to download and CPLD programming on production, traffic signal system to achieve the control process. EDA technology is used to design electronic products more advanced technology, designers can replace the complete electronic system design most of the work, but can directly from the process to amend the mistakes and system functions without the need for hardware circuits of support, both to shorten the development cycle, another significant cost savings by the electronic engineers of all ages. Achieving junction traffic signal system control many ways, using standard logic devic
Platform: | Size: 4096 | Author: jazvy | Hits:

[VHDL-FPGA-Verilogyibutongxin

Description: 本程序是用VHDL语言实现异步通信控制器, hao1.vhd为主程序,hao1.scf为仿真波形-this procedure is used VHDL asynchronous communication controller, mainly hao1.vhd procedures, hao1.scf for simulation waveforms
Platform: | Size: 704512 | Author: 陈华 | Hits:

[VHDL-FPGA-Verilogn_dc_motor

Description: vhdl实现的直流电机控制器 通用程序 对不同fpga/cpld,可能需要修改部分源代码。-VHDL achieved DC Motor Controller General of different procedures they simply/cpld. may need to amend some source code.
Platform: | Size: 2048 | Author: 刘挺 | Hits:

[VHDL-FPGA-Verilogsdramusevhdl

Description: sdram的vhdl实现 本文介绍了sdram的控制时序特征,并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
Platform: | Size: 84992 | Author: cxr | Hits:

[DocumentsUART(FPGA)

Description: 基于FPGA的串行通信UART控制器,采用VHDL语言编写,包含多个子模块。 在ISE或FPGA的其它开发环境下新建一个工程,然后将文档中的各个模块程序添加进去,即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Platform: | Size: 14336 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilogddr_sdram_controller_vhdl

Description: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Platform: | Size: 13312 | Author: hxwf801 | Hits:

[VHDL-FPGA-VerilogVGAimagecontrollor

Description: VGA图象显示控制器设计,实现在VGA显示器上显示图象.-VGA image display controller designed to achieve the VGA display shows images.
Platform: | Size: 1024 | Author: 刘叶 | Hits:

[VHDL-FPGA-Verilogsdram_control

Description: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱:wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Platform: | Size: 339968 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilognclight

Description: 利用硬件描述语言VHDL设计交通灯电路,设计一个十字路口交通灯控制器,东西、南北方向有红灯、黄灯、绿灯,持续时间分别为45、5、40秒。-use VHDL design of traffic lights at the circuit, the design of traffic lights at a crossroads controller East and West, North-South direction of a red light, yellow light, green light, the duration of 45, morphine seconds.
Platform: | Size: 1024 | Author: 空气 | Hits:

[VHDL-FPGA-Verilogsimple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现,Xilinx提供的.别谢我.-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-VerilogMVHDL

Description: 本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證-the parallel program for controlling flash ROM programs, rom flash can be read out information, After drawing CPLD controller will turn into VESA video signal and output to screen. The program has strong experience card
Platform: | Size: 4977664 | Author: 明華 | Hits:

[VHDL-FPGA-Verilogi2c_modular

Description: 本程式為使用VHDL撰寫的I2C controller modular, 使用者可以輕易的套用, 方便控制i2C的硬件. 也可以從code style了解I2C的spec. 動作模式. 極適用於初學者.-program for the use of the VHDL written I2C controller modular, Users can easily use, i2C convenient control of the hardware. can understand from the code style I2C in the spec. Action mode. very applicable to beginners.
Platform: | Size: 8192 | Author: 明華 | Hits:

[Graph DrawingVGAsingl

Description: fpga显示控制器,利用vhdl语言实现,只能显示8色。-fpga display controller, using vhdl language, the only shows that eight colors.
Platform: | Size: 1024 | Author: lyc | Hits:

[Other8051_ip_core

Description: 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
Platform: | Size: 339968 | Author: 大为 | Hits:

[Embeded-SCM Develop16bit_booth_multiplier_STG

Description: verilog程序,实现两个16bit数乘法,采用booth算法,基于状态机实现,分层次为datapath和controller两个子模块,testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-VerilogVHDL_TIMESET

Description: 本专题之研究,为使用硬件描述语言VHDL规划成自己所需要的硬件控制电路,配合上FPGA可程序化硬件设备中的相关模组,而发展出一套数位电子钟之控制器实现。-study of the topic, for the use of VHDL hardware description language into their planning the necessary hardware control circuit, coupled with FPGA hardware program to the relevant module, and the development of a set of digital electronic controller minute.
Platform: | Size: 26624 | Author: 王浩 | Hits:

[VHDL-FPGA-VerilogAsynCommCtrl

Description: 基于VHDL的串行异步通信电路的设计 包括串行发送器,异步接收器,以及控制器 vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
Platform: | Size: 4096 | Author: 飘来的南风 | Hits:

[VHDL-FPGA-Verilogxiyiji

Description: 洗衣机控制器,包括清洗、漂水、脱水等状态,vhdl-washing machine controller, including cleaning, bleaching water, dehydration state, vhdl
Platform: | Size: 4096 | Author: 飘来的南风 | Hits:

[OtherNAND_Controller_and_ECC_VHDL

Description: NAND Flash Controller & ECC VHDL Code-NAND Flash Controller
Platform: | Size: 22528 | Author: | Hits:

[VHDL-FPGA-VerilogCPLDxiaoche

Description: 智能机器小车主要完成寻迹功能,由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分,采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:
« 1 2 3 45 6 7 8 9 10 ... 46 »

CodeBus www.codebus.net